In the production of the monolithic integrated storage arrangements with their access circuits, as bit decoders, the reduction of power consumption is of prime importance. Originally, considerable efforts were made to reduce the power consumption of the storage cells themselves, and with the integration density increasing, it has also been attempted to cut down power consumption in the storage periphery, as, e.g., in the decoders.
To give an example: A pulse-driven decoder
is known from commonly assigned U.S. Pat. No. 3,573,758, filed on Feb. 27, 1969, by R. A. Henle and W. D. Pricer, which reduces power consumption in the control as well as in the decoder circuits of the monolithic integrated storage system. This is achieved in that the decoder circuits are maintained on a minimum current level in the absence of an access to the memory. Similarly, if no information is read out of or written into the storage system, the respective current levels are kept very low. The resulting power reduction merely lies in a predetermined period of the storage system, e.g., in an access-free period. Besides, there is the added disadvantage that compared with the circuits continuously operating with full current, such a circuit is very slow. Therefore, it is not advisable to use it in modern-day monolithic storage systems whose main feature, apart from the very low power dissipation, is maximum efficiency, i.e., high-speed access and high read/write speed. For complementary metal oxide semiconductor (CMOS) storage systems, such decoders are described in, e.g., IBM Technical Disclosure Bulletin Vol. 25, No. 4, September 1982, pp. 2135, 2136. CMOS storage systems requiring a very low current are described in, e.g., U.S. Pat. No. 4,251,876, filed on Nov. 3, 1978, and in the corresponding German Offenlegungsschrift No. 2,751,481. Addressed decoder circuits with a low power consumption are also described in U.S. Pat. No. 3,665,473 filed on Dec. 18, 1970. However, these well-known decoder circuits and CMOS storage systems do not offer any solution for storage systems which for the purpose of increased reliability are equipped with redundant word and/or bit lines. Such storage systems are basically described in IBM Technical Disclosure Bulletin Vol. 7, No. 9, February 1965, page 808, and commonly assigned U.S. Pat. No. 3,222,653, filed Sept. 18, 1961 by R. Rice, and German Pat. No. 2,144,870. Although these two latter patents cover storage systems with redundant word or bit lines, the ideas presented there are not applicable to present-day storage systems because they do not include the decoders for the redundant word lines in a concept for power reduction and increased speed. Modern semiconductor memories, particularly high speed CMOS storage systems with redundant word or bit lines with a very low power dissipation necessitate the full inclusion of decoders and drivers into this concept.